1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register and a pre-charge circuit thereof having stable pre-charge voltages.
2. Description of the Prior Art
FIG. 1 is a diagram illustrating a conventional shift register constructed by N-type Metal Oxide Semiconductor (NMOS) transistors. As shown in FIG. 1, the shift register 100 comprises an input end I, nodes Z and N, an output end O, a pre-charge circuit 110, an enabling control circuit 120, and three switches QN2, QN3, and QN4. The input end I of the shift register 100 receives driving signals from the shift register of the previous stage (not shown). The output end O of the shift register 100 outputs the driving signals of the shift register 100. The enabling control circuit 120 comprises a switch QN10 and an inverter INV1. The first end of the switch QN10 is coupled to the input end I, and the control end of the switch QN10 receives a clock signal CLK. The second and first ends of the switch QN10 are electrically coupled together according to the clock signal CLK. The input end of the inverter INV1 is electrically coupled to the second end of the switch QN10, and the output end of the inverter INV1 is electrically coupled to the node N for outputting the inverted signal received on the input end of the inverter INV1 to the node N. The pre-charge circuit 110 comprises a switch QN1. The control end of the switch QN1 is electrically coupled to the input end I, the first end of the switch QN1 is electrically coupled to the input end I, and the second end of the switch QN1 is electrically coupled to the node Z. The switch QN1 transmits the signal received on the input end I to the node Z so as to pre-charge the node Z. The control end of the switch QN2 is electrically coupled to the node N, the first end of the switch QN2 is electrically coupled to the node Z, and the second end of the switch QN2 is electrically coupled to the output end O. The control end of the switch QN3 is electrically coupled to the node Z, the first end of the switch QN3 receives the clock signal XCK, and the second end of the switch QN3 is electrically coupled to the output end O. The logic “1” of the clock signals XCK and CLK are set to be 7.5 Volts as the high voltage VDD, and the logic “0” of the clock signals XCK and CLK are set to be 0 Volts as the low voltage VSS. The voltage setting for the logic levels “0” and “1” of the clock signals are disclosed as an example. The control end of the switch QN4 is electrically coupled to the node N, the first end of the switch QN4 is electrically coupled to the voltage source VSS, and the second end of the switch QN4 is electrically coupled to the output end O, and the clock signals CLK and XCK have opposite polarity to each other and have the same frequency.
FIG. 2 is a timing diagram of the shift register 100. As shown in FIG. 2, when the input end I receives the driving signal from the shift register of the previous stage (not shown), the voltage on the input end I rises to the voltage VDD, and the pulse width is a half period of the clock signal XCK. The driving signal from the shift register of the previous stage is transmitted through the pre-charge circuit 110 to the node Z and through the enabling controller 120 to the node N. Meanwhile, the first half period of the clock signal XCK is at logic “0”. Since the pre-charge circuit 110 is constructed by the switch QN1 (NMOS), the voltage on the node Z is lowered by a source-to-drain voltage VDS of the switch QN1. In this condition, the voltage VDS is the threshold voltage VTH1 of the switch QN1, and the threshold voltage VTH1 is assumed to be 2.5 Volts. Thus, the voltage on the node Z is 5 Volts (VDD−VTH1). Since the enabling controller 120 is constructed by the switch QN10 and the inverter INV1, the voltage on the node N is lowered to 0 Volts, and stays the same for one period of the clock signal XCK. As shown in FIG. 2, because the voltage on the node N is 0 Volts, the switches QN2 and QN4 are turned off. In the second half period of the clock signal XCK, in which the clock signal XCK stays at logic “1”, the switches QN1, QN2, and QN3 are all turned off, and thus the electric charge accumulated on the node Z has no current path to discharge. The voltage on the node Z is further raised by a voltage VDD to be 12.5 Volts (2VDD−VTH1=2×7.5−2.5) when the clock signal XCK on the first end of the switch QN3 rises from logic “0” to logic “1”, because an intrinsic capacitor C1 exists between the second end of the switch QN3 and the control end of the switch QN3. Therefore, the switch QN3 is turned on and the voltage on the output end O rises to the voltage VDD as the driving signal for the shift register 100. Next, when the voltage on the node N again rises to the voltage VDD, the switches QN2 and QN4 are turned on, which lowers the voltage on the output end to be the voltage VSS.
According to the above description, when the shift register 100 outputs driving signals, the voltage on the node Z is (2VDD−VTH1), the voltage on the output end O is VDD, and thus the gate-to-source voltage VGS of the switch QN3 should be 5 Volts (VGS=2VDD−VTH1−VDD=VDD−VTH=7.5−2.5). However, the driving ability of the output end O of the shift register 100 is related to the gate-to-source voltage (VGS) of the switch QN3. That is, the higher the voltage VGS of the switch QN3 is, the higher the driving ability of the output end O of the shift register 100 is. The threshold voltage VTH varies with fabrication process. Therefore, the voltage VGS of the switch QN3 derived from the equation (VDD−VTH1) varies with the fabrication process, and thus the driving ability of the shift register 100 is severely affected.
FIG. 3 is a diagram illustrating a conventional shift register fabricated with P-type Metal Oxide Semiconductor (PMOS) transistors. As shown in FIG. 3, the shift register 200 comprises an input end I, nodes Z and N, an output end O, a pre-charge circuit 210, an enabling control circuit 220, and three switches QP2, QP3, and QP4. The input end I of the shift register 200 receives driving signals from the shift register of the previous stage (not shown). The output end O of the shift register 200 outputs the driving signals of the shift register 200. The enabling control circuit 220 comprises a switch QP10 and an inverter INV2. The first end of the switch QP10 is electrically coupled to the input end I, and the control end of the switch QP10 receives a clock signal XCK. The switch QP10 electrically couples the second end of the switch QP10 to the first end of the switch QP10 according to the clock signal XCK. The input end of the inverter INV2 is electrically coupled to the second end of the switch QP10, and the output end of the inverter INV2 is electrically coupled to the node N for outputting the inverted signal received on the input end of the inverter INV2 to the node N. The pre-charge circuit 210 comprises a switch QP1. The control end of the switch QP1 is electrically coupled to the input end I, the first end of the switch QP1 is electrically coupled to the input end I, and the second end of the switch QP1 is electrically coupled to the node Z. The switch QP1 transmits the signal received on the input end I to the node Z so as to pre-charge the node Z. The control end of the switch QP2 is electrically coupled to the node N, the first end of the switch QP2 is electrically coupled to the node Z, and the second end of the switch QP2 is electrically coupled to the output end O. The control end of the switch QP3 is electrically coupled to the node Z, the first end of the switch QP3 receives the clock signal CLK, and the second end of the switch QP3 is electrically coupled to the output end O. The logic “1” of the clock signals XCK and CLK is set to 7.5 Volts as the high voltage VDD, and the logic “0” of the clock signals XCK and CLK is set to 0 Volts as the low voltage VSS. The voltage setting for the logic levels “0” and “1” of the clock signal are disclosed as an example, which can be designed as desired. The control end of the switch QP4 is electrically coupled to the node N, the first end of the switch QP4 is electrically coupled to the voltage source VDD, and the second end of the switch QP4 is electrically coupled to the output end O. However, since the shift register 200 employs the PMOS process, the switches QP1˜QP4, and QP10 are PMOS transistors. Additionally, the clock signals CLK and XCK have opposite polarity to each other and have the same frequency.
FIG. 4 is a timing diagram illustrating the shift register 200. As shown in FIG. 4, when the input end I receives the driving signal from the shift register of the previous stage (the voltage on the input end I falls from the voltage VDD to the voltage VSS and the pulse width is a half period of the clock signal CLK), the driving signal from the shift register of the previous stage is transmitted through the pre-charge circuit 210 to the node Z and through the enabling controller 220 to the node N. Meanwhile, the first half period of the clock signal CLK is at logic “1”. Since the pre-charge circuit 210 is constructed by the switch QP1 (PMOS), the voltage on the node Z is raised by a source-to-drain voltage VDS of the switch QP1. In this condition, the voltage VDS is the threshold voltage VTH2 of the switch QP1, and the threshold voltage VTH2 is assumed to be 2.5 Volts. Thus, the voltage on the node Z is 5.5 Volts (VDD−VDD+VTH2). Since the enabling controller 220 is constructed by the switch QP10 and the inverter INV2, the voltage on the node N is raised from 0 Volts to the voltage VDD, and stays the same for one period of the clock signal CLK. As shown in FIG. 4, because the voltage on the node N is VDD, the switches QP2 and QP4 are turned off. In the second half period of the clock signal CLK, which the clock signal XCK keeps at logic “1”, the switches QP1, QP2, and QP3 are all turned off, and thus the electric charge accumulated on the node Z has no current path to dispense. The voltage on the node Z is further lowered by a voltage VDD and to be −2.5 volts (VTH1−VDD=2.5−5) when the clock signal CLK on the first end of the switch QP3 falls from logic “1” to logic “0” because an intrinsic capacitor C2 exists between the second end of the switch QP3 and the control end of the switch QP3. Therefore, the switch QP3 is turned on and the voltage on the output end O falls to 0 Volts as the driving signal for the shift register 200. Next, when the voltage on the node N again falls to 0 Volts, the switches QP2 and QP4 are turned on, which raises the voltage on the output end O to be the voltage VDD.
It can be seen from the above that when the shift register 200 outputs driving signals, the voltage on the node Z is (−VDD+VTH2), the voltage on the output end O is 0 Volts, and thus the gate-to-source voltage VGS of the switch QP3 should be −5 Volts (VGS=−VDD+VTH2−0=−7.5+2.5). However, the driving ability of the output end O of the shift register 200 is related to the VGS of the switch QP3. That is, the higher the voltage VGS of the switch QP3 is, the higher the driving ability of the output end O of the shift register 200 is. The threshold voltage VTH varies with fabrication process. Therefore, the voltage VGS of the switch QP3 derived from the equation (−VDD+VTH2) varies with the fabrication process, and thus the driving ability of the shift register 200 is severely affected.